A flash memory device is a type of electrically erasable programmable read-only memory (EEPROM) and is used for nonvolatile storage of data. Flash memory is being increasingly used to store execution codes and data in portable electronic products, such as computer systems.
Flash memory devices are programmed and erased by sequences of operations (or algorithms). A program algorithm normally involves sequentially applying a programming pulse and a program-verify pulse to a set of memory cells of a flash memory device. This is repeated until the set of memory cells is programmed. An erase algorithm typically comprises a pre-programming cycle, an erase cycle, and a soft program cycle. The pre-programming cycle of the erase algorithm puts each memory cell in a programmed state by applying a program pulse to each row of memory cells. The soft program cycle or heal cycle corrects any over-erased memory cells after the erase cycle has been completed by applying a soft program pulse to the over-erased memory cells. This is often referred to as compaction.
A control circuit (or algorithm controller) is used to manage the various steps of program and erase algorithms. For one application, the algorithm controller executes a code stored on the controller and interacts with hardware devices of the flash memory device, such as memory cell address counters, pulse counters, pulse duration counters, or the like, that are external to the algorithm controller for causing the hardware devices to perform various functions. Moreover, the algorithm controller causes hardwired actuators of the memory device that are external to the algorithm controller to send actuator signals to analog voltage generators of the memory device for controlling the voltage generators during program, erase, or compaction operations. The actuator signals also configure switches and control program verify operations. One problem with hardware devices and hardwired actuators is that many of them are of a fixed design for a particular application and cannot be readily reconfigured or updated for other applications, thereby limiting versatility and reusability of the flash memory device design.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for alternative algorithm controllers for memory devices, such as flash memory devices.